In computer systems, a central processing unit (CPU) accesses memory by providing an address which indicates a unique location of a group of memory cells which collectively store the accessed data element. The CPU initiates what is referred to as a bus cycle by providing the address to an address bus, and one or more control signals to signal that the address is valid and the bus cycle has begun. A read/write control signal then indicates whether the access is to be a read access or a write access. Subsequently, a data element is either read from a data bus if the bus cycle is a read cycle, or provided to the data bus if the bus cycle is a write cycle. A memory device to accommodate such accesses is connected to the address and data buses, and provides data to the data bus during a read cycle, or stores data on the data bus during a write cycle, at a location indicated by the address on the address bus. This type of bus cycle requires at least two clock cycles, and typically may require four or more clock cycles.
In an effort to improve efficiency, computer architects have developed several additional modes for faster accesses. For example, in some integrated circuit memory devices, several storage cells are accessed simultaneously and their contents are held temporarily in a buffer. Typically, the addresses of these "extra" storage cells differ from the original access address by only one or two bits. However subsequent accesses to these cells can be accomplished by simply executing access cycles without changing the access address. In the art, such memories are referred to as "nibble mode". In some other integrated circuit memories, a portion of the original access address can be assumed for one (or more) subsequent accesses, so that only the least significant portion of the address needs to be decoded, etc. Thus, once the original access has been completed, subsequent accesses to "related" storage cells will be significantly quicker. These types of memories are sometimes referred to as "column mode" or "static column". In memory systems constructed using such enhanced performance memory devices, the effect is to allow the memory to sustain rapid transfers of several operands in "bursts" of m, where m is two (2) to the n power, n being an integer and characteristic of the selected memory device.
One example of the usefulness of a burst access is when the CPU has an on-chip cache. When the CPU accesses a line of the cache that needs to be updated (known as a cache miss), the cache requires a set of data words to be read from external memory. This operation is known as a cache line fill. The cache line may be any arbitrary number of bytes or words of data, but typically is 4 words, where a word is typically 32 bits long. By having the burst mode available, the cache line fill operation to external memory consists of a four bus cycle ("four beat") burst cycle. This four-beat burst cycle is efficient, requiring the cache to control the bus for a minimum number of clock cycles, and allows the cache line to be filled in a continuous access to reduce or eliminate coherency problems that could occur if another device accesses the memory location in between the cache's accessing the words of the cache line.
However, as time goes on, integrated circuit density will increase, adding complexity. There exists a need to accommodate this increase in integration and to have ever more flexible modes of burst operation. These problems are met with the present invention, whose features and advantages will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.